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library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity D1_C2 is
port(
clk:in std_logic;
s0,s7 : out STD_LOGIC
);
end D1_C2;
--}} End of automatically maintained section
architecture D1_C2 of D1_C2 is
begin
process(clk)
begin
if(clk='1') then s0<='1';s7<='1';
else s0<='0';s7<='0';
end if;
end process;
end D1_C2;
-- clk=0.5hz
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Chi tiết xin liên hệ:
Nguyễn Duy Tân
Email: nguyenduytan1909@gmail.com hoặc duytandhdt3k5@gmail.com
Yahoo: nguyenduytan1909
Skype: Tannd1909
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-----------------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity D1_C2 is
port(
clk:in std_logic;
s0,s7 : out STD_LOGIC
);
end D1_C2;
--}} End of automatically maintained section
architecture D1_C2 of D1_C2 is
begin
process(clk)
begin
if(clk='1') then s0<='1';s7<='1';
else s0<='0';s7<='0';
end if;
end process;
end D1_C2;
-- clk=0.5hz
Chi tiết xin liên hệ:
Nguyễn Duy Tân
Email: nguyenduytan1909@gmail.com hoặc duytandhdt3k5@gmail.com
Yahoo: nguyenduytan1909
Skype: Tannd1909
FaceBook:Nguyễn Duy Tân
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