Download Code Here
-----------------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity D6_C2 is
port(
SI : in STD_LOGIC_VECTOR(3 downto 0);
SO : out STD_LOGIC_VECTOR(3 downto 0)
);
end D6_C2;
architecture D6_C2 of D6_C2 is
begin
process(SI)
begin
SO<=SI;
end process;
end D6_C2;
-- clk=1Mhz
---------------------------------------------------------------------------------------------------------
Chi tiết xin liên hệ:
Nguyễn Duy Tân
Email: nguyenduytan1909@gmail.com hoặc duytandhdt3k5@gmail.com
Yahoo: nguyenduytan1909
Skype: Tannd1909
FaceBook:Nguyễn Duy Tân
-----------------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity D6_C2 is
port(
SI : in STD_LOGIC_VECTOR(3 downto 0);
SO : out STD_LOGIC_VECTOR(3 downto 0)
);
end D6_C2;
architecture D6_C2 of D6_C2 is
begin
process(SI)
begin
SO<=SI;
end process;
end D6_C2;
-- clk=1Mhz
---------------------------------------------------------------------------------------------------------
Chi tiết xin liên hệ:
Nguyễn Duy Tân
Email: nguyenduytan1909@gmail.com hoặc duytandhdt3k5@gmail.com
Yahoo: nguyenduytan1909
Skype: Tannd1909
FaceBook:Nguyễn Duy Tân
No comments:
Post a Comment